1. Field of the Invention
The present invention relates to a signal processor for encoding and decoding various kinds of data, particularly, image data.
2. Related Background Art
Various types of apparatuses have been developed to enable to transmit data at a relatively low transmission rate by encoding huge volumes of various data to decrease the volumes of data.
For example, for a digital VTR for recording image data in a recording medium such as a magnetic tape, there has been established a standard which specifies to compress input image data of approximately 124 MBps to approximately 25 MBps as large as ⅕ of the former volume.
In the digital VTR based on such standard as described above, the input data is quantized after DCT conversion and compressed by variable-length encoding the quantized data. In addition, the quantizing step for quantizing the data is varied in accordance with various parameters and the rate is controlled so that the volume of data which has been variable-length encoded is fixed.
The MPEG standard, which stipulates compression of input image data by using forecast encoding with inter-frame shift compensation and further compression of the image data by using DCT, quantizing and variable-length encoding as described above, is currently being established and various devices such as a CD-ROM and others which conform to this standard are developed.
An encoding/decoding device used in various apparatuses as described above uses a plurality of independent memories.
That is, for example, in a case of the digital VTR, a video memory for tentatively storing input image data and a track memory for storing coded data for which encoding has been completed before recording are required and, in the prior art, these memories have been independently provided.
An apparatus based on the MPEG standard is provided with a plurality of independent memories such as input buffer memories and reference buffer memories for compensating movement.
However, if a plurality of such memories are separately provided and independently controlled, such provision of the memories has been a cause of increased costs of the signal processor as a whole.
An object of the present invention made in view of the above actualities is to provide a signal processor capable of reducing costs thereof.
An embodiment of the present invention made to fulfill the above object is to provide a signal processor which comprises a plurality of processing means for carrying out various steps of processing which are different from one another, a memory means provided in common for the plurality of processing means and a control means for controlling access between the steps of processing and the memory means wherein the control means carries out address control in different terms in accordance with the steps of processing.
Another embodiment of the present invention made to fulfill the above object is to provided a signal processor which comprises a plurality of processing means for carrying out various steps of processing which are different from one another, a memory means provided in common for the plurality of processing means and a control means for controlling access between the steps of processing and the memory means wherein the control means prefers accessing of data according to a higher processing priority of the data and executes time-sharing processing.
In addition, a further another embodiment of the present invention made to fulfill the above object is to provide a signal processor which comprises a plurality of processing means for carrying out various steps of processing which are different from one another, a memory means provided in common for the plurality of processing means, a means for setting parameters in a plurality of types of data to be processed, and a control means for carrying out address control between the steps of processing and the memory means wherein the control means makes the address control different in accordance with the parameters conforming to the data.
According to the above embodiments, the control means for carrying out access control between the steps of processing and the memory means is provided and various types of processing can be carried out even with a single memory by address control in terms of different units in accordance with the steps of processing by means of the control means.
The above embodiments enable to carry out high speed processing even when a single memory means is used simultaneously for various kinds of processing by making a control means, which is provided for carrying out access control between various steps of processing and the memory means, preferentially perform access operation of data with higher processing priority and executing time sharing processing.
In addition, according to the above embodiments, a means for setting the parameters in accordance with a plurality of kinds of data to be processed and a control means for carrying out address control between the steps of processing and the memory means are provided and the control means is easily applicable to data in various formats by varying the address control in accordance with the parameters conforming to the above respective data.
An object of the present invention made in view of the above actualities is to provide a signal processor capable of reducing costs and processing the data at a processing speed demanded even when a common memory means is used.
An object of another embodiment of the present invention made to attain the above object is to provide a signal processor comprising a plurality of processing means for which are different from one another, a memory means provided in common for the plurality of processing means, a mode designating means for designating an operation mode, and a control means for carrying out access control between the processing means and the memory means according to the operation mode to be set by the mode designating means wherein the control means varies the priority of the access control in accordance with the operation mode.
The embodiment as described above enables to carry out an optimum control for respective operation modes by varying the priority of the access control in conformity to the operation mode and therefore a high speed operation according to the purpose of operation.
In addition, the present invention made in view of the above-described actualities is intended to provide a signal processor capable of reducing costs and high speed access in accordance with the contents of processing.
A further another embodiment according to the present invention is intended to provide a signal processor, which is characterized in that the signal processor is provided with a plurality of processing means for carrying out various kinds of processing which are different from one another in a specified data unit and a memory means which is provided in common for the respective processing means and has an input/output part capable of high speed transfer of the data in the specified unit, and the specified unit of data enabling high speed transfer in the input/output part is adapted to be applicable to the data unit for the respective processing means.
This embodiment enables to carry out high speed read/write operation by adapting the specified unit of, data enabling high speed transfer in the input/output part to be applicable to the data unit for the respective processing means.
Other objects and characteristics of the present invention will be clearly known from the following description and the accompanying drawings.